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2020 Intern- F10 ADTS ATE Study and development of clean bevel in 3D NAND – MICRON – Singapore

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Req. ID: 143069
_Title :_ Study and development of clean bevel in 3D nand Non-Volatile
Memory
_Description :_ Due to complexity of memory structure- there are a lot of
new processes and tools being introduced resulted new type of defects which
affecting wafer quality. In this project- student will have exposure on most
advance semiconductor machines- gain experience on the state-of-the-art fab
operation and attain process development/troubleshooting knowledge as require
working with process engineering team on improvement work.

_Scope :_
Perform data collection on WiseCam- G6/G7 API- KMAC Bevel Image and KMAC Backsid

Collaboration with process engineers for process improvemen

Students will be able to learn how to use statistical tools- fab specific applications and software for process- perform design of experiment to optimize process

_Deliverable :_

Line comb movie of 1XX layers technode
Develop Best Known Method to have clean bevel and clean backside

All qualified applicants will receive consideration for employment without
regard to race- color- religion- sex- sexual orientation- gender identity-
national origin- veteran or disability status.

2020 Intern – F10 PEE ADTS (Dry Etch) – MICRON – Singapore

On: By: admin

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Req. ID: 140902
Description: Dry etching refers to the removal of material- typically a
masked pattern of semiconductor material- by exposing the material to a
bombardment of ions that dislodge portions of the material from the exposed
surface. The etching rate and the plasma ion directionality are heavily
depends on tool design and configuration. In this project- students will have
the hands-on opportunity to work on advanced industry-leading Etch Tool- gain
1st hand experience of Semiconductor Fab operations. Students will work with
Process Engineering team and Tool Installation team on new tool
characterization and qualification.
Scope: Perform process characterization for Dry Etch tools with tunable
voltage edge rings and develop optimized process conditions. Collaborate wit

the process and equipment engineers to study and understand the effect

between the plasma etch condition and hardware design. Student will be able t

learn how to use statistical tools- fab-specific applications and software fo

operations/datamining; as well as perform Design of Experiment (DOE) to
optimize the process/equipment.

Deliverable: Characterization data on the tunable edge ring across parts
lifetime. Develop Best Known Method to reduce variation on this tool type and
automate the process monitoring.

All qualified applicants will receive consideration for employment without
regard to race- color- religion- sex- sexual orientation- gender identity-
national origin- veteran or disability status.